Approximate arithmetic has become a prominent choice for applications tolerating inaccurate results. By relaxing accuracy requirements, circuit complexity, delay, and energy consumption can be significantly reduced. In this paper,an approximate parallel multiplier design, based on simplified logic is being proposed by us.This is carried out by calculating product terms, then compressing the adjacent bits of same column based on the required cluster depths and thereby mapping the resulting product terms to achieve a less number of product rows. Thus, a reduction in silicon area is expected to be achieved. Multipliers with varying bit widths viz., 8-bit, 16-bit and 32-bit are designed using Verilog. Post-simulationresults done using Xilinx ISE 12.1 tool, show that nearly 50% reduction in silicon area could be achieved compared to accuratemultiplier design. These multipliers could be used in power-constrained computing, multimedia applications, scientific computing etc.

Keywords : approximate arithmetic, cluster depth, power-constrained computing

Author : Harika Gandamaneni, Dr.V.Thrimurthulu

Title : A 32-BitArea-Efficient Approximate Parallel Multiplier Design

Volume/Issue : 2019;01(3)

Page No : 1-7

Packet classification is a critical technology for secure communication and networking. Security tools and Internet services use packet sorting technology that includes checking packets against predefined rules stored in a workbook. Fulfill software solutions available for classifying unwanted and efficient processing of wired speed in high-speed networks. Ternary Content Addressable Memory (TCAM), Bit-Vector (BV), Field Sharing Bit Vector (FSBV). In this article, we recommend a simple and efficient memory method for classifying packets on the Xnor portal, instead of the lookup tables called the XnorBV approach. The packet header fields of the IP addresses and the protocol layer are categorized by the Xnor gateway against a predefined set of rules that also support bitrates '1', '0' and '*', while the port numbers in the packet header support range match the port numbers with minimum and maximum values. The proposed XnorBV architecture is independent of the ruleset properties and supports multidimensional classification.

Keywords : Ternary Content Addressable Memory (TCAM), Bit-Vector (BV), Field Sharing Bit Vector (FSBV)

Author : Anil Kumar Reddy Kannapu, M.Adiseshaiah

Title : High SpeedPacket Classification Using XnorBV

Volume/Issue : 2019;01(3)

Page No : 8-15

The past few years have Seen a major changes in huge data volumes in big data world. Spark as in memory cluster computing to analyse the large amount of data in a frame work. Spark offers a rich set of big data application through the programming interface. Spark programming framework provide an effective open source solution for managing and analyze the big data. Now a day’s engineering education plays a key role in Andhra Pradesh, India.Engineerin education growing importance of day to day usage of learning management system. The LMS and technical education system has made significant contributions to produce one of the largest technical usages of engineering education students in Andhra Pradesh. This paper discussing the Spark working model procedure as well as Learning management’s activities by the students and their information behaviour.

Keywords : Human information interaction, Big data, Spark, RDD,LMS

Author : RAJESH KUMAR.P, B. VIJAYA, V.SAMBA SIVA, A N SREEDHAR

Title : AN EFFICIENT APACHE SPARK FRAMEWORK ANALYSIS FOR ENGINEERING STUDENT’S INFORMATION BEHAVIOUR

Volume/Issue : 2019;01(3)

Page No : 16-24

This paper helps us to discuss about approximate Reverse Carry Propagate Adder (RCPA), In RCP adders the carry signal propagates in counter down flow manner. I.e. it flows from the maximized prioritized bit to the least prioritized bit. Henceforth the carry i/p signal has the greater significance then the o/p carry. This way of carry propagation increases the steadiness in presence of delay versions, here in this paper we are discussing about the three different designs of RCPA cells with different delay, energy, and accuracy configurations, and also we use a few hybrid structure within the n bit adder design were least half of the adder design is carried out with this RCPA and most considerable half will be introduced by way of using some accurate high pace adder like KoggeStone adder that may decorate the adder speed. The Hybrid adders realized utilizing those systems are studied and as compared people with conventional approximate adders with Xilinx ISE 14.7 Verilog HDL coding.

Keywords : Approximate adder, Digital Signal Processing (DSP), Reverse Carry Propagate adder (RCPA), Kogge Stone adder (KSA)

Author : P. RAMYA, DR. V. THRIMURTHULU, G. DILLIRANI

Title : DESIGN AND IMPLEMENTATION OF HIGH SPEED HYBRID ADDER WITH REVERSE CARRY PROPAGATE ADDER

Volume/Issue : 2019;01(3)

Page No : 25-33

IoT has been shown as a big potential for qualifying and improving healthcare services; such as monitoring at anytime and anyplace. These services acquire various bio- signals using different sensors, including electroencephalogram (EEG), electrocardiogram (ECG), electrical signal of the heart, electromyogram (EMG), electrical signal of muscles, Respiratory Rate (RR), and body motion. The collected information from these sensors can be processed, stored, or broadcast to a remote device (e.g. Cloud server). This paper provides an overview of the main medical sensors in IoT and a review of the current state-of- the-art of IoT projects, and technologies required for healthcare services. The paper specifically, focuses on the using of IoT technologies in the healthcare area nowadays. A conclusion regarding the current stage of development and open issues are presented.

Keywords : Internet of Things (IoT); Healthcare; Alzheimer diseases; Cloud Computing; M2M; Quality of Life (QoL); Embedded Systems; Sensors; RFID; NFC; Big data

Author : Ch. Bala Subramanyam, B Sunil Kumar

Title : Technologies of Internet of Things for Healthcare services

Volume/Issue : 2019;01(3)

Page No : 34-42

Reversible Logic has become one of the most promising research areas in recent decades and its applications in various technologies; As a CMOS with low consumption, nanotechnology and optical processing. The main purpose of designing reversible logic is to reduce quantum cost, depth of circuits, and number of waste products. The purpose of this document is to provide a framework, understanding, and review of reversible doors. In this document, various logical gates and their applicability to logical design are discussed. In addition, a brief overview of the comparison between reversible circuits based on various parameters is presented. The combination of decoders, comparators, full adders and multiplexers is designed using Fredkin Gate, CNT and GatePres, which offer better quantum costs than other reversible gates. Reversible logic circuits are designed and implemented using the VERILOG code, and the simulation results are obtained in Simulux ISE version 14.1.

Keywords : CMOS, Fredkin Gate, CNT and GatePres, VERILOG code

Author : D.Neelima, S.Ali Asgar, Dr.V.Thrimurthulu,

Title : A NOVEL REVERSIBLE DECODER FOR DESIGN AND SYNTHESIS OF COMBINATIONAL CIRCUITS

Volume/Issue : 2019;01(3)

Page No : 43-50

Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. So this Low Power Pulse Triggered Flip Flop reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems. In this method an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is used. Pulse-triggered FF (P-FF) is a single-latch structure which is more popular than the conventional transmission gate (TG) and master–slave based FFs in high-speed applications.

Keywords : Flip-flop (FF), low power, pulse-triggered.

Author : S.Ali Asgar, Dr. P.Krishnamurthy

Title : REDUCED POWER FLIP FLOP DESIGN BASED ON SIGNAL FEED THROUGH SCHEME

Volume/Issue : 2019;01(3)

Page No : 51-58

Artificial intelligence (AI) is defined as a field of science and engineering concerned with the intelligent behavior. It is the subfield of computer science as it has enhanced the human life in many areas. AI has recently bested human performance in several domains, and there is a great hope in healthcare. The healthcare system handles very huge amount of data which is very hard to analyze through traditional methods. The success of AI in healthcare promises better prevention, detection, diagnosis, and treatment of diseases. Polycystic ovarian syndrome (PCOS) is a hormonal disorder for women menstrual cycle at the stage of reproductive age. Women with PCOS find their menstrual cycle comes every 21 days or more often. Sometimes have fewer periods (fewer than eight in a year) or women with PCOS stop having menstrual period. This can leads to infertility and development of cysts in the ovaries. Symptoms of PCOS include Irregular menstrual cycle, weight gain, darkening of skin, Thinning hair on the scalp, Diabetes and High blood pressure. Early diagnosis and treatment are recommended. AI is capable of “learning” features from very large amount through clinical practice to diagnosis this diseases. AI has the capability to increase its accuracy by self-correct aspects. In this paper, applications of AI in the detection of PCOS, segmentation and classification are presented.

Keywords : Artificial intelligence, polycystic ovarian syndrome (PCOS), detection of PCOS, segmentation and classification.

Author : V. Deepika

Title : Applications of Artificial Intelligence Techniques in Polycystic ovarian syndrome Diagnosis

Volume/Issue : 2019;01(3)

Page No : 59-63

This brief proposes an on-line straightforward test system for discovery of inert hard blames which create in first info first yield supports of switches amid field operation of NoC. The method includes rehashing tests intermittently to forestall collection of deficiencies. A model usage of the proposed test calculation has been incorporated into the switch channel interface and on-line test has been performed with manufactured self-comparable information activity. The execution of the NoC after expansion of the test circuit has been explored as far as throughput while the region overhead has been considered by integrating the test equipment. Likewise, an on-line test strategy for the directing rationale has been proposed which considers using the header bounces of the information activity development in transporting the test designs.

Keywords : Straightforward test, NoC, Switch Channel, On-line test

Author : R.Durga naik, Dr .M.Rambabu naik , B.Balaji Naik,

Title : MODERN APPROACH OF DETECTING PERMANENT FAULTS FOR MULTIPURPOSE PROCESSOR DESIGN OF NOC RELEVANCES

Volume/Issue : 2019;01(3)

Page No : 64-76

Now a day’s the Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With theMost efficient reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests.By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of independent of the design size and also provides an additional on-chip debugging signal visibility for each register. It is backward compatible to the standard full scan designs and with a minor enhancementexisting test pattern generators and simulators can be used and also discussed for the solution of adding built-in self test (BIST) and massive parallel scan chains with the proposed design.The design and implementation of single cycle access test structure for logic test is functionally verified using Xilinx ISE simulator 13.1 and the generated bit stream file is implemented in Spartan 3E XC3S50OE FPGA board, which demonstrates the all-possible combinations of proposed single cycle access test structure for logic test on its LCD display. The pre layout and post layout synthesis and its physical design are performed using cadence RTL Compiler and SOC Encounter tools respectively, with the optimized area, power, and delay.

Keywords : Built-in self test (BIST), LCD, RTL Compiler, SOC

Author : G.Manthru Naik, J.Brahmaiah Naik

Title : An Efficient Novel Approach Paradigm of Single Cycle Switching Access Structure to Eliminate the Peak Power Consumption Problem

Volume/Issue : 2019;01(3)

Page No : 77-85

We consider a survey on scheduling of real time on multicore processors. In this survey, we observe that the cores are distributed for the incoming task according to their workloads. Depends on the task workload the cores may be splitted into big and small core. The big cores are having more Floating Point and multiply accumulate(FPMAC) units also the small cores having less number of FPMAC units. We can use the big core for complicated tasks and small one for easy tasks. Because of this dividing of cores we can use cores efficiently and the output will be reliable one. The survey outlines fundamental results about multicore processor real-time scheduling that hold independent of the scheduling algorithms employed. The scheduling algorithm such as LTF scheduling, EDF scheduling, Priority scheduling are used according to their algorithm.

Keywords : Multicore Processor, Realtime schedulling, Schedulling Algorithms.

Author : Akhila.B, Lordwin Cecil Prabaker.M and Brahmaiah Naik.J

Title : Survey of Real Time Task Scheduling Algorithms for Multicore Processors

Volume/Issue : 2019;01(3)

Page No : 86-94

With increasing rate of crime, protecting our loved ones and our belongings has become important. Such situations can be solved by exploiting the latest functionalities that current ability makes it easier to automate the process of security. Automation of security can be achieved by designing an application on Roseberry Pi through various sensors such IR and Gas sensors for detection of any intruder and harmful gases in the house, upon detection an SMS will be sent to the owner of the house through GSM. The loads like lights and fan will be ON. The home automation system differs from other system by allowing the user to operate the system from anywhere around the world through internet connection. In this paper we present a Home Automation system(HAS) using Raspberry PI that employs the integration of cloud networking, wireless communication, security etc., to provide the user with remote control of various lights, fans, and appliances within their home and storing the data in the cloud. The system will automatically change on the basis of sensors’ data. This system is designed to be low cost and expandable allowing a variety of devices to be controlled .It connects all the devices through GPIO pins and is known as the heart of the entire system.

Keywords : Sensors, Rospberry Pi, Switch, IR, GPIO, GSM.

Author : Mrs.S.Venkata lakshmi, C.Govardhan

Title : Providing Security for Home Appliances by IoT

Volume/Issue : 2019;01(3)

Page No : 95-103

In today’s worlds the demand of data transmission with high bandwidth and speed is increased to overcome which technology of communication is moving towards 5G due to their compact features. This 5G uses the mmwave frequency range in this experiment we design a rectangular microstrip antenna of patch type and simulate it. In this research, a 38 GHz frequency range from Ka band is taken. The compact structure of patch antenna diameters is of 6.285 mm × 7.235 mm × 0.5 mm. but the resonating frequency range is 27.954 GHz to our proposed antenna having a loss of that is return loss of about of -13.48 dB, and with 900MHz bandwidth, also 10dB gain and 80% efficient is obtained after simulation. For matching the patch of radiation and feed line of 50 ohm microstrip we use insect feed technique of transmission line. In fabrication of this antenna lithography technique is used on Roger RT Duroid 5880 substrate which has high tolerance with tangent loss of 0.0009, height is about 0.4mm and dielectric constant of 2.2 is used. By using CST Microwave Studio we simulate our design of antenna in proposed geometry.

Keywords : CST, millimeter wave, Microstrip patch antenna, 5G, ka band, dielectric constant.

Author : MD. JAVEED AHAMMED, R. SAMBASIVA NAYAK, NAYEEMUDDIN MOHAMMED

Title : SIMULATION OF RECTANGULAR MICROSTRIP PATCH ANTENNA FOR RANGE OF Ka BAND FREQUENCY

Volume/Issue : 2019;01(3)

Page No : 104-112

Most low-power electronics, such as remote sensors and implantable devices are powered by batteries. However, even long-lasting batteries have a limited lifespan and must be replaced every few years. The replacements become costly when there are hundreds of sensors in remote locations. Energy harvesting technologies, on the other hand, provide unlimited operating life of low-power equipment and eliminate the need to replace batteries where it is costly, impractical, or dangerous. Most energy harvesting applications are designed to be self-sustaining, cost-effective, and to require little or no servicing for many years. In addition, the power is used closest to the source, hence eliminating transmission losses and long cables. If the energy is enough to power the device directly, the application or device powered by the energy can operate battery less. Tyre pressure monitoring systems (TPMS) are becoming increasingly important to ensure safe and efficient use of tyres in the automotive sector and powered by batteries. These pressure sensors mounted an inside of the rim and the batteries are not exchangeable. When a battery reaches the end of its life span the whole sensor has to be replaced. In order to provide a maintenance free and battery less sensor solution there is growing interest in using energy harvesting technologies to provide power to TPMS.

Keywords : Energy harvesting, piezoelectric sensor, CMOS, Low power, TPMS.

Author : N.VITHYALAKSHMI, P.GEETHA, M.VISHNU VARDHAN REDDY, S.RAKESH

Title : LOW POWER CMOS PIEZOELECTRIC ENERGY HARVESTING CIRCUIT FOR VEHICLE TYRE PRESSURE SENSOR

Volume/Issue : 2019;01(3)

Page No : 113-121

Now a day’s antennas plays a major role in communications where its demand is getting increased to feed the needs in this paper the basic Multiple Input Multiple Output (MIMO) antenna is designed which is of 8 matrix sizes for 5G devices which are high in range and having higher bandwidth. These antennas are of size occupies 3 x 4 mm2 each which is implanted on top most layer of substrate plate in H-shaped rotated Patch form. Where the total size of substrate we take is of 31.2 x 31.2 x 1.57 mm3, size with dielectric constant of size 2.2. We place total 8 MIMO antennas in substrates top layer and the substrates bottom is a ground plane where this ground plane is of Electromagnetic Band Gap (EBG) design only for obtaining efficiency and gain enhanced. For avoiding spurious radiation if any we feed out substrate from the bottom layer through vias. These kinds of antennas have resonation at 27 GHZ with bandwidth of 6DB. In the whole band width of antennas attained gain is of more than 7 dB that has a high range 8dB. Similarly the efficiency we obtained in these antennas is about 65% than the highest of 93%. CST microwave design tools are used for these antennas design and the simulation results have given the better performance of the MIMO antennas which makes them suitable of 5G technology.

Keywords : 5G, EBG, High Gain, MIMO, Efficiency, Patches

Author : R.SambaSiva Nayak Nayeemuddin Mohammad B.Satyanarayana MD.Javeed Ahammed

Title : MIMO Based Rectangular Micro Strip Antenna for 5th Generation Communication System

Volume/Issue : 2019;01(3)

Page No : 122-129

The deployment of Wireless Sensor Networks (WSN) in the field of military, battlefield, healthcare applications etc has seen a plethora of growth towards variety of sensory devices. Irrespective of different locations, the sensor nodes has to do its task. Hence, the dynamic wireless sensor networks should ensure better quality of sensor nodes that covers wider network area and additional services in relative to static WSNs systems. By doing so, it requires secure data communication among the sensor nodes in wireless environment. Key Management is the recent security concept enabled to provide secure communication between sender and receiver nodes. In this paper, we have proposed efficient key updates systems between the nodes. In any scenario, the nodes may join or leaves the network environment which facilitates to initiate a secret key between intended sender and intended receiver. A certificate less key secrecy system is designed for secure communication in wireless links. By designing so, we have addressed the issues like node authentication, data confidentiality, and data integrity. Experimental analyses have shown the effectiveness of proposed system.

Keywords : Wireless Sensor Networks, Dynamic networks, Sensor nodes, Sensory devices, Key management, Key updates and Node authentication.

Author : A Basi Reddy, , B Ramakantha Reddy , P Krishna Kishore , K Prathima

Title : ANALYSIS OF KEY MANAGEMENT AND CRYPTOGRAPHY IN WIRELESS SENSOR NETWORKS

Volume/Issue : 2019;01(3)

Page No : 130-136

Controlling power flow in modern power systems can be made more flexible by the use of recent developments in power electronic and computing control technology. The Unified Power Flow Controller (UPFC) is a Flexible AC transmission system (FACTS) device that can control all the three system variables namely line reactance, magnitude and phase angle difference of voltage across the line. The UPFC provides a promising means to control power flow in modern power systems. Essentially the performance depends on proper control setting achievable through a power flow analysis program. The paper presents a reliable method to meet the requirements by developing a Newton-Raphson based load flow calculation through which control settings of UPFC can be determined for the pre-specified power flow between the lines. The proposed method keeps Newton-Raphson Load Flow (NRLF) algorithm intact and needs (little modification in the Jacobian matrix). A MATLAB program has been developed to calculate the control settings of UPFC and the power flow between the lines after the load flow is converged. Case studies have been performed on IEEE 5-bus system to show that the proposed method is effective. These studies indicate that the method maintains the basic NRLF properties such as fast computational speed, high degree of accuracy and good convergence rate.

Keywords : UPFC; FACTS (Statcon, TCSC, TCRP); Optimal power flow algorithm (N-R Method); Mat lab

Author : M C V SURESH

Title : Optimal controlling power flow in Transmission System by using UPFC

Volume/Issue : 2019;01(3)

Page No : 137-147

With each upgrade in Internet as far as speed and transmission capacity, IOT (Internet Of things) is taking the showcase on another hub and thumping the entryway with new chances of inventions. This paper discusses a vitality sparing electrical system observation and supervision framework using IOT. An enormous measure of vitality is devoured by lighting apparatuses, so making improved productivity and brisk shortcoming identification is a critical challenge. In this work, two unique model methodologies are pursued relying upon the idea of application. For little regions or restricted premises IEEE 802- 2016 standards remote innovation is utilized where every one of the machines is associated with a typical Wi-Fi network. In the subsequent model like road light shaft where number of machines becomes just in one course, wired setup is utilized to stay away from range issue.

Keywords : Electrical systems, IOT, IEEE 802-2016 standard, supervision system etc.

Author : Jyothilal Nayak Bharothu, K V V N Bhaskar, P Srikanth & B N V Satish Kumar Kolla

Title : Electrical System Observation and Supervision using IOT

Volume/Issue : 2019;01(3)

Page No : 148-156

A microgrid will take part in a vital role in the future, since it will decrease the tension by the rising electricity demands, as compared to the constraints forced by power plants and transmission lines. Hence, identifying the optimal operating point of any distributed generators (DGs) in a microgrid leads them to identifying the optimal operation of any generator in them of cost minimization efficiency maximization. This paper proposes a novel algorithm to resolve the optimal operating point of distributed generators. In this algorithm, the new droop characteristic slopes (frequency vs. active power and voltage vs. reactive power) of the inverter will be detected of the optimized point. Conventionally, inverter based DGs droop characteristic slopes have a steady slope in their maximum and minimum capacity in the deferent function mode of microgrid. If any alter is necessary, the slope will be selected random. To reduce the deviation of droop characteristic slopes and the other objectives, the multi-objective optimization algorithm can be used. The multi-objective optimization is used in this paper, can give the logical choice to determine the new droop characteristic slopes in optimized point with least variation.

Keywords : Microgrid, distributed generators (DGs), distributed energy resources (DERs), algorithm, droop characteristics etc

Author : Jyothilal Nayak Bharothu, DrJ.Srinu Naick and P Hemanth Kumar

Title : Electrical systems, IOT, IEEE 802-2016 standard, supervision system etc.

Volume/Issue : 2019;01(3)

Page No : 157-166

Embedded systems that are employed in safety-critical applications require highest reliability. External watchdog timers are used in such systems to automatically handle and recover from operation time related failures. Most of the available external watchdog timers use additional circuitry to adjust their timeout periods and provide only limited features in terms of their functionality. This paper describes the architecture and design of an improved configurable watchdog timer that can be employed in safety-critical applications. Several fault detection mechanisms are built into the watchdog, which adds to its robustness. The functionality and operations are rather general and it can be used to monitor the operations of any processor based real-time system. This paper also discusses the implementation of the proposed watchdog timer in a Field Programmable Gate Array (FPGA). This allows the design to be easily adaptable to different applications, while reducing the overall system cost. The effectiveness of the proposed watchdog timer to detect and respond to faults is first studied by analyzing the simulation results.

Keywords : FPGA, Watch Dog Timer (WDT), Hardware Description Language (HDL), Input and Output Interface, Verilog and VHDL.

Author : R.Haripriya R.Sentamilselvam

Title : Performance of FPGA in an Enhanced Level of Watchdog Timer

Volume/Issue : 2019;01(3)

Page No : 167-180

The differently abled mute people cannot converse with the others through the sign language. This paper proposes a device that will help them to overcome their challenges and remove the communication barrier between the mute and the common people. Here, an embedded glove senses the movements through the flex sensors that detect the different patterns of motion of fingers. The embedded glove needs to be worn on the hand by the needy and depending on the variations in the finger movement; the device will convert it into voice and this expressive system can be customized based on the specific individual's requirement. The device can sense each and every movement of the fingers. The change in the resistance of flex sensors leads to the change in voltage levels, which helps to different signs. This paper is useful for specially abled, speech-impaired and paralyzed patients who could not communicate properly.

Keywords : Sign language, flex sensors, gesture, finger movement, Micro Controller

Author : Dr. P. Geetha, Dr. N. Vithyalakshmi, K.Khaleel & T.Litheesh

Title : Sign Language to Text and Speech Converter- A Sensor-based gesture recognition system

Volume/Issue : 2019;01(3)

Page No : 181-185

The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly-exact computation of DCT require floating point arithmetic, are multiplier intensive, and accumulate round-off errors. Recently proposed fast algorithm arithmetic cosine transform (ACT) calculates the DCT exactly using only additions and integer constant multiplications, with very low area complexity, for null mean input sequences. The ACT can also be computed non-exactly for any input sequence, with low area complexity and low power consumption, utilizing the novel architecture described. However, as a trade-off, the ACT algorithm requires 10 non-uniformly sampled data points to calculate the eight-point DCT. This requirement can easily be satisfied for applications dealing with spatial signals such as image sensors and biomedical sensor arrays, by placing sensor elements in a non-uniform grid. In this work, hardware architecture for the computation of the null mean ACT is proposed, followed by a novel architecture that extend the ACT for non-null mean signals. All circuits are physically implemented and tested using the Xilinx XC6VLX240T FPGA device and synthesized for 45 nm TSMC standard-cell library for performance assessment.

Keywords : Discrete Cosine Transform, Trade-Off, Arithmetic Cosine Transform(ACT), Low Area Complexity and Low Power Consumption.

Author : Naganaik Mudhavathu , Dr. P.Karpagavalli

Title : Low Complexity of VLSI Computational Architectures for the ACT Techniques

Volume/Issue : 2019;01(3)

Page No : 186-194

The penetration of photovoltaic (PV) systems has been increased worldwide. The output power generation of photovoltaic (PV) has an intermittent nature due to cloud transients. Consequently, distributed PV systems with their intermittent feature can seriously affect the voltage regulation in distribution systems. In this paper, an optimal voltage control (OVC) method for unbalanced distribution networks (UDNs) with PV and plug-in hybrid electric vehicles (PHVs) is proposed. In this paper, a method is proposed to mitigate voltage fluctuations due to PV by simultaneously optimizing the reactive power of the PV inverters and charging/discharging power of the plug-in hybrid electric vehicles (PHEV). This OVC method considers different types and configurations of voltage regulators, and three-phase and single-phase step voltage regulators (SVRs). The use of this new objective yields a high reduction in the voltage fluctuations. The artificial bee colony (ABC) algorithm is utilized to optimally solve the real-time optimization problem while considering the constraints of the distribution system, PV inverters, and PHEVs. The simulation results on the 33-bus distribution system demonstrate the effectiveness of the proposed method for mitigating the voltage fluctuations during a high fluctuating generation profile of PV.

Keywords : Unbalanced distribution networks, Voltage fluctuation, distribution system, Photovoltaic (PV) and artificial bee colony ABC algorithm

Author : MURALII KRISHNA.V, CHENNURI VENUGOPAL

Title : Optimal Voltage Control Method for Unbalanced Distribution System with PV and Phevs Using Artificial Bee Colony Algorithm

Volume/Issue : 2019;01(3)

Page No : 195-199

Social network analysis emerged as an important research topic in sociology decades ago, and it has also attracted scientists from various fields of study like psychology, anthropology, geography and economics. This paper focuses on building a recommendation algorithm for C2C (Consumer-to-Consumer) e-commerce business model by considering special features of C2C e-commerce websites. In this paper, users and their transactions considered as a network based on link prediction using a graph based technique. This is an important task in social network analysis is used to build the recommender system. The proposed tow-level recommendation algorithm, rather than topology of the network, uses nodes’ features like category of items, ratings of users, and reputation of sellers. The links predicted can be presented as recommendations to the user. This paper also focuses on how graph algorithm can be used to improve recommendation in ecommerce websites. The method incorporates semantic recommendation using overlap technique based in graph. The results show that the proposed model can be used to predict a portion of future trades between users in a C2C commercial network.

Keywords : C2C e-commerce, Social network analysis, link prediction, Graph based algorithm, overlap technique

Author : AAREPU LAKSHMAN, Dr. YOGESH KUMAR SHARMA, Dr. B.M.G. PRASAD

Title : SOCIAL NETWORK ANALYSIS OF C2C E-COMMERCE RECOMMENDER SYSTEM BASED ON LINK PREDICTION BY EMPLOYING GRAPH BASED APPROACH

Volume/Issue : 2019;01(3)

Page No : 200-207

Classification of cancer based on gene expression has provided insight into possible treatment strategies. Analysis of gene expression is important in many fields of biological research in order to retrieve the required information. It provides accurate prediction providing better treatment to the patients. One of major challenges is to discover how to extract useful information from huge dataset. A high-capacity system was developed to monitor the expression of many genes in parallel. Microarrays prepared by high-speed robotic printing of complementary DNAs on glass were used for quantitative expression measurements of the corresponding genes. Because of the small format and high density of the arrays. Cancer classification based on microarray has become a popular research topic in bioinformatics, which can be used to detect subtypes of cancers and produce therapies. Gene selection may provide insights into understanding the underlying mechanism of a specific biological phenomenon. Also, such information can be useful for designing less expensive experiments by targeting only a handful of genes. Finally, incorporating diverse types of genomic data (e.g., protein-protein interaction data and gene expression) increase the prediction accuracy as compared to using gene expression.

Keywords : Classification, gena expression, cDNA array

Author : Sanku Rajendra Kumar, Dr. Anil Kumar

Title : Framework of Classification with Microarray data Prediction Cancer Using Gene Express

Volume/Issue : 2019;01(3)

Page No : 208-212