Upendar S 00 01 To represent very large or small values large range is required as the integer representation is no longer appropriate These values can be represented using the IEEE754 standard based floating point representation This paper presents high speed ASIC implementation of a floating point arithmetic unit which can perform addition subtraction multiplication division functions on 32bit operands that use the IEEE 7542008 standard Pre normalization unit and post normalization units are also discussed along with exceptional handling All the functions are built by feasible efficient algorithms with several changes incorporated that can improve overall latency and if pipelined then higher throughput The algorithms are model in Verilog HDL and the RTL code for adder subtractor multiplier are synthesized using HDL DESIGNER SERIES AND XILINX Copyright (c) World Journal of Pharmaceutical Seiences. All rights reserved 2026