DESIGNING OF SUBTITUTION -BOX WITH MULTIBIT PARITY DETECTION METHOD
This paper presents novel approach for designing of AES S-box using combinational logic using Verilog and simulated in Xilinx ISE 13.2.AES is data encryption standard which uses same at Encryption as well as for decryption. AES uses Substution box was divided into five blocks and are designed by Combinational blocks. So that we can easily analyse faults which are caused by natural/malfunctioning faults.
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